Real-Time Demonstration of a Digital Interpolator-Free Clock Recovery for an FPGA-Based PM-QPSK Coherent Optical Receiver

A low-complexity digital interpolator-free clock recovery architecture with analog and digital coprocessing is proposed. Wide-range sampling clock offset is captured by using timing phase error spectrum analysis at open-loop low-speed operation mode, and the accurate tracking of high-speed sampling clock frequency and phase is achieved by adjusting the reference clock source of ADCs with a direct digital synthesizer (DDS) module in a feedback closed-loop operation. The feasibility and the stability of the clock recovery scheme are verified in a 10-Gbps data rate PM-QPSK modulation field programmable gate array (FPGA)-based homodyne coherent receiver with a commercial DDS chip. Compared with the traditional all-digital scheme with linear and Lagrange interpolators, the receiver sensitivity of the proposed scheme at BER of 1×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> improves 1.5 and 0.4 dB due to the absence of ripple and lowpass effect introduced by digital interpolator, and the utilization of ALMs, logic register, and hardware multiplier is reduced by 79%, 81%, 83% and 81%, 84%, 92%, respectively. Moreover, the proposed coprocessing method is further validated and compared in an adaptive equalization and clock recovery joint scheme. The biggest contribution of this work is the clever use of analog and digital coprocessing to achieve stable and signal distortion-free clock recovery with lower cost, lowest power, and minimum logic resource consumption.