An efficient new design of nano-scale comparator circuits using quantum-dot technology

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata (<i>QCA</i>) is a promising nanotechnology solution for solving <i>CMOS</i>-related issues. The <i>4-dot</i> squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares <i>2 voltages</i> or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed <i>1-bit</i> design employs <i>35</i> quantum cells in a <i>0.</i>04 μm² compact layout space. Also, the proposed <i>2-bit</i> design uses <i>173</i> cells in a <i>0.</i>19 μm2 compact layout area. These circuits, which are built across three layers of <i>90-degree</i> cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented <i>1-bit</i> comparator circuit uses <i>3</i> majority gates with three inputs. The first output signal in <i>1-bit</i> comparator is generated after <i>0.75 clock phases</i> and in <i>2-bit</i> design after <i>1.25 clock phases</i>. <i>QCADesigner-E</i> evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.