Solutions enabling advanced packaging and heterogeneous integration

In the initial stage of advanced packaging, it was applied to CSWLP (Chip-Scale-Wafer-Level-Package) mainly for the package form-factor reduction. However, advanced packaging is used not only for the package size reduction but also for many remarkable features including Fan-out wafer level packages that are used for mobile application processor to increase interconnect counts and reduce chip height. 2.5D silicon interposer technology is also used for Graphics Processing Units (GPU) and Artificial Intelligence (AI) chips to interconnect System-on-Chips (SoC) and cache memory to provide wide bandwidth. Advanced packaging will also play a key role in the upcoming heterogeneous integration. Canon developed the first i-line stepper for advanced packaging in 2011. Since then, we have expanded our tool lineup to support customer demands with developments supporting large size packages and panel-level packaging. In this paper, we compare advantages between wafer-level packaging and panel-level packaging. Furthermore, we will report our low distortion patterning solution of our latest packaging stepper, FPA-5520iV LF2 option.