Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation

The accuracy of embedded non-volatile memory (eNVM) in-memory computing (IMC) designs is primarily limited by analog non-idealities. This article introduces a magnetoresistive random-access memory (MRAM) IMC macro in 22-nm featuring offset-compensating current sensing (OCCS) to reduce the static analog-to-digital converter (ADC) column mismatch and a low-overhead statistical error compensation (SEC) block compensating for non-linearity arising due to bitline/source-line (BL/SL) wire parasitics. Both assist in enhancing the bank-level compute signal-to-noise-plus-distortion ratio (SNDR). As the inner dimension of the matrix-vector multiplication (MVM) increases, the compute SNDR reduces due to increased location-dependent non-linearity arising from BL/SL wire parasitics. An SEC-enabled SNDR boost of 2.7–6 dB is obtained over different operating points. This boost can be balanced to achieve a substantial <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> reduction in energy per 1-b operation while incurring a modest SEC energy overhead of 0.8% and area overhead of 12.2%. Finally, the study demonstrates an SEC-enabled increase in neural network (NN) accuracy from 74.8% to 82.0% for CIFAR-10 by last layer mapping of ResNet-20, without resorting to noise-aware training.