Frequency Investigation of SiC MOSFETs C-V Curves with Biased Drain

SiC MOSFETs still suffers from some open issues, such as the high density of defects existing at the SiC/ SiO 2 interface. In order to characterize such interface, a non-destructive investigation technique should be employed. In this work, we investigate the measurement of Gate capacitance with biased Drain. More in detail, the effect of frequency on such curves is considered. The analysis is performed using both in experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region which reduces its height as frequency increases.