Non-Linear Gate Stack Effect on the Short Circuit Performance of a 1.2-kV SiC MOSFET
In this paper, the effect of a non-linear dielectric gate stack on the short-circuit performance of a 1.2 kV SiC MOSFET was analyzed through TCAD simulations. Starting from the TCAD model of a commercial 1.2 kV, its standard gate oxide was replaced with a stack formed by oxide and a non‑linear dielectric, characterized by a temperature dependent permittivity. This variation on temperature can be exploited to reduce the current conducted during short-circuit events, lowering the temperature reached through the device by about 30%, without affecting its static and dynamic performance.
Authors
- Luca Maresca (ORCID: https://orcid.org/0000-0003-4660-5163)
- Giovanni A. Salvatore (ORCID: https://orcid.org/0000-0002-8983-3257)
- Alessandro Borghese (ORCID: https://orcid.org/0000-0002-6285-4242)
- Michele Riccio (ORCID: https://orcid.org/0000-0002-5926-4911)
- Andrea Irace (ORCID: https://orcid.org/0000-0003-1400-8380)
- Marco Boccarossa (ORCID: https://orcid.org/0000-0002-6912-5413)
- Giovanni Breglio (ORCID: https://orcid.org/0000-0002-9350-5483)
Institutions
- Ca' Foscari University of Venice (IT)
- Federico II University Hospital (IT)
- University of Naples Federico II (IT)
Publication Details
- Journal
- Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena
- Published
- 2024-08-23
- DOI
- https://doi.org/10.4028/p-50znan
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00