Expanding the Pareto Front of Ferroelectric Field-Effect Transistors With a Dual-<i>k</i> Spacer

In this study, a novel dual-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacer ferroelectric field-effect transistor (FeFET) structure is proposed. By adopting the dual-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacer for the first time in FeFET, the target memory window (MW) of 0.5 V is achievable at a write voltage of 5 V. The write voltage shows a 2.0-V reduction from 7 V for the low-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacer FeFET (L-FeFET) and a 1.0-V reduction from 6 V for the high-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacer FeFET (H-FeFET). The write power of the proposed FeFET was 25.9% lower than that of the low-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> FeFET and H-FeFET. These improvements significantly expand the Pareto front and mitigate the effects of trapped charge. The dual-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> spacer FeFET structure is a promising candidate for low-voltage and low-power operations.