Optimized Quantum Circuit of AES With Interlacing-Uncompute Structure

In the post-quantum era, the security level of encryption algorithms is often evaluated based on the quantum resources required to attack AES. In this work, we make thoroughly estimations on various performance metrics of the quantum circuit of AES-128/192/256. Firstly, we introduce a generic round structure for in-place implementation of the AES algorithm, maximizing the parallelism between nonlinear components. Specifically, when employed as an encryption oracle, our structure reduces the <inline-formula><tex-math notation="LaTeX">$T$</tex-math></inline-formula>-depth from <inline-formula><tex-math notation="LaTeX">$2rd$</tex-math></inline-formula> to <inline-formula><tex-math notation="LaTeX">$(r+1)d$</tex-math></inline-formula>. Furthermore, by leveraging the properties of block-cyclic matrices, we present an in-place implementation circuit for MixColumn with depth 10, utilizing 105 CNOT gates. In relation to the S-box, we have assessed its minimum circuit width at different <inline-formula><tex-math notation="LaTeX">$T$</tex-math></inline-formula>-depths and provide multiple versions of circuit implementations for a depth-width trade-off. Finally, based on our optimized S-box circuit, we conduct a comprehensive analysis of the implementation complexity of different round structures, where our structure exhibits significant advantages in terms of low <inline-formula><tex-math notation="LaTeX">$T$</tex-math></inline-formula>-depth.