HGNAS: <u>H</u>ardware-Aware <u>G</u>raph <u>N</u>eural <u>A</u>rchitecture <u>S</u>earch for Edge Devices

Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Nevertheless, the research community has primarily focused on improving model expressiveness, lacking consideration of how to design efficient GNN models for edge scenarios with real-time requirements and limited resources. Examining existing GNN models reveals varied execution across platforms and frequent Out-Of-Memory (OOM) problems, highlighting the need for hardware-aware GNN design. To address this challenge, this work proposes a novel hardware-aware graph neural architecture search framework tailored for resource constraint edge devices, namely HGNAS. To achieve hardware awareness, HGNAS integrates an efficient GNN hardware performance predictor that evaluates the latency and peak memory usage of GNNs in milliseconds. Meanwhile, we study GNN memory usage during inference and offer a peak memory estimation method, enhancing the robustness of architecture evaluations when combined with predictor outcomes. Furthermore, HGNAS constructs a fine-grained design space to enable the exploration of extreme performance architectures by decoupling the GNN paradigm. In addition, the multi-stage hierarchical search strategy is leveraged to facilitate the navigation of huge candidates, which can reduce the single search time to a few GPU hours. To the best of our knowledge, HGNAS is the first automated GNN design framework for edge devices, and also the first work to achieve hardware awareness of GNNs across different platforms. Extensive experiments across various applications and edge devices have proven the superiority of HGNAS. It can achieve up to a <inline-formula><tex-math notation="LaTeX">$10.6\boldsymbol{\times}$</tex-math></inline-formula> speedup and an <inline-formula><tex-math notation="LaTeX">$82.5\%$</tex-math></inline-formula> peak memory reduction with negligible accuracy loss compared to DGCNN on ModelNet40.

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Publication Details

Journal
IEEE Transactions on Computers
Published
2024-08-23
DOI
https://doi.org/10.1109/tc.2024.3449108
Citations
9
Primary Topic
ICT Impact and Policies
Type
article
Field-Weighted Citation Impact
2.88

Funders

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article

HGNAS: <u>H</u>ardware-Aware <u>G</u>raph <u>N</u>eural <u>A</u>rchitecture <u>S</u>earch for Edge Devices

Chunming Hu, Jianlei Yang, Yumeng Shi, Weisheng S. Zhao et al.
9 citations
IEEE Transactions on Computers
ICT Impact and Policies
2.88
article

HGNAS: <u>H</u>ardware-Aware <u>G</u>raph <u>N</u>eural <u>A</u>rchitecture <u>S</u>earch for Edge Devices

Chunming Hu, Jianlei Yang, Yumeng Shi, Weisheng S. Zhao, Cenlin Duan, Yingjie Qi, Ao Zhou, Tong Qiao
article en
9 citations

Abstract

Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Nevertheless, the research community has primarily focused on improving model expressiveness, lacking consideration of how to design efficient GNN models for edge scenarios with real-time requirements and limited resources. Examining existing GNN models reveals varied execution across platforms and frequent Out-Of-Memory (OOM) problems, highlighting the need for hardware-aware GNN design. To address this challenge, this work proposes a novel hardware-aware graph neural architecture search framework tailored for resource constraint edge devices, namely HGNAS. To achieve hardware awareness, HGNAS integrates an efficient GNN hardware performance predictor that evaluates the latency and peak memory usage of GNNs in milliseconds. Meanwhile, we study GNN memory usage during inference and offer a peak memory estimation method, enhancing the robustness of architecture evaluations when combined with predictor outcomes. Furthermore, HGNAS constructs a fine-grained design space to enable the exploration of extreme performance architectures by decoupling the GNN paradigm. In addition, the multi-stage hierarchical search strategy is leveraged to facilitate the navigation of huge candidates, which can reduce the single search time to a few GPU hours. To the best of our knowledge, HGNAS is the first automated GNN design framework for edge devices, and also the first work to achieve hardware awareness of GNNs across different platforms. Extensive experiments across various applications and edge devices have proven the superiority of HGNAS. It can achieve up to a <inline-formula><tex-math notation="LaTeX">$10.6\boldsymbol{\times}$</tex-math></inline-formula> speedup and an <inline-formula><tex-math notation="LaTeX">$82.5\%$</tex-math></inline-formula> peak memory reduction with negligible accuracy loss compared to DGCNN on ModelNet40.

IEEE Transactions on ComputersVol. 73(12)
Beihang University (CN)
National Natural Science Foundation of China, Fundamental Research Funds for the Central Universities
Openalex Percentile: Top 8%
ICT Impact and Policies
2.88
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