A 180–194-GHz Power Amplifier Co-Designed With a Power-Combining End-Fed Slot Antenna Array in 65-nm CMOS

This article presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$180\mathit - 194$ </tex-math></inline-formula>-GHz eight-way (four-way differential) power amplifier co-designed with a power-combining antenna array in a 65-nm CMOS technology. The power-combining antenna array consists of four closely placed end-fed slot antennas, providing a low input impedance, a high radiation efficiency, and a compact layout. The proposed power-combining scheme can increase the output power of a power amplifier without causing the increment of the loss of the amplifier output matching/combining network, which is not possible for a conventional on-chip power combiner with a path number larger than 4 (two-differential). In the measurement, the power amplifier achieves a measured small-signal gain of 21.6 dB, a saturated radiated power of 18.2 dBm, a 1-dB-compression radiated power of 12.6 dBm, and a peak power added efficiency (PAE) of 6.6% at 184 GHz, with the antenna loss included. The measured directivity and saturated effective isotropic radiated power (EIRP) of the chip packaged with a hyperhemispherical silicon lens are 22.7 dBi and 40.9 dBm, respectively, at 184 GHz. The measured 3-dB bandwidth of the power amplifier is 14.1 GHz.