Enhancing Characteristics of 1700-V SiC VDMOSFETs: Strategic Integration of Cell Design and Process Optimization

In this article, we present an investigation into the influence of cell designs and process optimizations on 1700-V 4H-silicon carbide (SiC) vertical double-implanted MOSFETs (VDMOSFETs). The device characteristics of the VDMOSFET were carefully examined considering various design and process perspectives. We designed and fabricated five different cell topologies—linear, square, hexagonal, staggered square (SS), and circular cells—to characterize their performance. It was found that the JFET width, a crucial cell design parameter, significantly dominated the specific on-state resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {on,sp}}$ </tex-math></inline-formula>) once it reached a specific critical threshold value. Only through JFET-related process enhancement, the JFET effect could be relaxed, contributing less to the total on-resistance. Among the various cell types, the circular cell exhibited the most favorable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {on,sp}}$ </tex-math></inline-formula> value and showed less JFET effect due to a higher JFET density. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {on,sp}}$ </tex-math></inline-formula> can be achieved to below 4 m<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega \cdot $ </tex-math></inline-formula> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, regardless of cell designs, after JFET process optimization. Furthermore, we observed that the linear cell had the highest gate resistance compared to the other cell types. Additionally, the linear cell demonstrated lower input capacitance than the other cells. Lastly, we performed dynamic double pulse tests (DPTs) on the fabricated VDMOSFETs to demonstrate their switching characteristics with high power capability. It was concluded that the linear cell VDMOS is suitable for high switching applications, while square, hexagonal, and SS cell VDMOSFETs are better suited for lower switching applications that require high output current. The circular cell is suitable for applications with medium-frequency and high-output current demands.