Assessing DC and RF Reliability of SiGe HBTs Stress-Engineered Using Dummy BEOL Layers

The present work demonstrates, for the first time, the impact of back-end-of-line (BEOL) design on the electrical reliability of SiGe heterojunction bipolar transistors (HBTs). Mixed-mode and high-current stress were performed for four different SiGe HBT variants designed with varying levels of dummy metal over-layers. The avalanche multiplication factor was found to be insensitive to changes in the BEOL, and thus the classical mixed-mode degradation was found to be similar across all BEOL variants. Meanwhile, high-current stress showed that adding more dummy metal layers alleviated the current gain and base current density degradation by 30% and 100%, respectively. Both the mechanical stress and temperature differences due to additional dummy metal layers were investigated using calibrated technology computer-aided design (TCAD) simulations. To assess RF implications, small-signal transition frequency (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}$ </tex-math></inline-formula>) improved by about 21%, and large-signal power added efficiency (PAE) increased by about 4% while the RF breakdown remained unchanged. The present study sheds light on the impact of reliability on dummy BEOL design, as well as its potential performance enhancement for circuit design in a manner that incurs no additional concern for electrical reliability under nominal conditions.