Comprehensive Understanding of Schottky Barrier Tunneling FET Built upon Ultrathin Silicon Nanowire for Monolithic 3D Integration

A Schottky barrier tunneling field-effect transistor (SBT FET) built upon catalytically grown ultrathin silicon nanowires (SiNWs) offers a preferable low-temperature routine to construct top device layers for monolithic three-dimensional (3D) integration technology, but there still remain several peculiar electronic transport behaviors that need to be better understood. In this work, a high-performance SBT FET was fabricated based on orderly SiNWs grown via the in-plane solid–liquid–solid (IPSLSL) mechanism, achieving an Ion/Ioff ratio of 106 and a SS of 150 mV/dec. The as-fabricated device, with SBT contacts between SiNWs and Pt/Au source-drain electrodes, was analyzed and compared to a three-dimensional numerical model built via the TCAD simulator to extract the actual energy band profile and the bias distribution in the SBT FET, as well as the hole carrier mobility in the catalytic SiNW channels. This comparative investigation also reveals the limiting factors for the SBT transport and explains well the observed peculiar channel-bias-dependent drain-induced barrier-lowering (DIBL) behavior. These results provide an in-depth understanding of SBT FET and lay a solid basis for its future applications in high-performance logic and in-memory computing in advanced 3D architecture.