An 11.2-pJ/bit Reconfigurable Dynamic Chaotic Encryption ASIC for IoT

Chaotic encryption is applied as a lightweight symmetric cryptography in Internet of Things (IoT). In symmetric encryption, system security depends on the randomness of the encryption sequence. However, the chaotic algorithm cannot be efficiently implemented with high precision in IoT resource-constrained circumstance. The cyclic effect of the algorithm under limited precision makes the sequence randomness not enough, while the exponential enhance in overhead by increasing the precision is not satisfy the lightweight goal. Therefore, a reconfigurable chaotic encryption ASIC with dynamic precision is proposed. Initially, a reconfigurable chaotic combination strategy based on multidimensional perturbations is proposed to improve sequence randomness. Second, a reconfigurable architecture with resource sharing and specified computation units are designed to effectively reduce the overhead of the algorithm hardware implementation. In addition, dynamic precision architecture is employed to provide tradeoff between precision and power consumption. Finally, the security results demonstrate that the scheme achieves satisfactory various metrics. The synthesis results by using 65-nm CMOS technology shows that its area is only 11.8k <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm { m}}^{2}$ </tex-math></inline-formula>, with 179.6-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>W power and 11.2-pJ/bit energy efficiency at 50 MHz, which achieves lower overhead compared to the existing hybrid chaotic encryption designs.