DESIGN AND OPTIMAL ANALYSIS IMPLEMENTATION OF DIGITAL PHASE LOCK LOOP WITH RING VCO USING 45nm CMOS TECHNOLOGY

The Thesis describe Digital PLL is the advanced Phase Lock Loop (PLL) design and implementation.using the 45nm CMOS Technology in CADENCE Virtuoso ADE (Analog Design Environment) .The circuit design of DPLL with the main blocks of Phase Frequency detector (PFD), loop filter ,Voltage Control Oscillator (VCO).The output of the VCO in going in the PFD through the feedback network.The various parameters performance obtained with the aid of several simulation kinds.While their designing process mainly work with the power supply, frequency range, power dissipation, dead zone size of PFD and the area.The circuit performance will effect with the leakages, some unwanted signals such as noise and improper or mismatching in the device.The operating frequency of the VCO is 8.5Ghz.The simulation results are shown and used for the maintenance system in satellites, high performance or speed and very low power PLL applications.The DPLL consume 485mW of power at the 2V supply voltage.At this supply voltage the VCO produce oscillations and the VCO phase noise is -100dbm and periodic steady state (PSSR) is 7.23dbm at this frequency