Design and Implementation of FinFET and GnrFET Based Dynamic Path Auto Configurable Joint Adder Subtractors

Adders and subtractors are essential to many integrated circuits (IC), including microprocessors, and micro controllers.However, using complementary metal oxide semiconductor (CMOS) and field effect transistor (FET) technology to make conventional adders and subtractors increased transistor count and power consumption.So, this effort begins with hybrid adder-subtractor designs using FinFET and graphene nano-ribbon FET(GnrFET) nano technologies.Initial development of an enhanced full adder with carry prediction (EFOCP) based on multiplexer logic with rapid carry-output selection reduced sum estimation delays.The considerable reduction in carry-output selection time led to this finding.The dynamic path auto-configurable adder (DPAA) selects high-speed and low-speed carry propagation channels using the EFOCP module.The DPAA was also used to create a two-complement based dynamic path auto-configurable subtractor (DPAS).Last, the dynamic path auto-configurable joint adder-subtractor (DPAJAS) combines DPAA and DPAS.Compared to existing approaches, the proposed DPAJAS design reduces Total Energy Consumption (TEC) by 23.3%,Total Path Delay (TPD) by 17.9%, and Carry Out Rise Delay by 18.2%.It also reduces Carry Out Fall Delay (COFD) by 19.4%, Sum Rise Delay (SRD) by 18.2%, and Sum Fall Delay by 18.3%.Finally, the proposed DPAJAS reduces Average Power Consumption (APC) 17.6%.These enhancements demonstrate the higher performance and efficiency of the proposed EFOCP, DPAA, DPAS, and DPAJAS designs.