A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing

Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based analog standard cell library in a commercially available 65 nm process that allows analog IC designers to use synthesis tools with an abstracted design mindset similar to large-scale digital design. We fabricate the test cells, which include filters with programmable corners, an analog classifier, and an arbitrary waveform generator (AWG); experimentally characterize FG programming; and experimentally demonstrate the performance of the standard cells. Overall, the standard cells achieve a similar or smaller footprint than previous approaches while leveraging the benefits of FG programming at smaller technology nodes.

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Publication Details

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2024-08-19
DOI
https://doi.org/10.1109/tvlsi.2024.3432916
Citations
5
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.92
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article

A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing

Pranav O. Mathews, Jennifer Hasler, Swagat Bhattacharyya, Afolabi Ige et al.
5 citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog and Mixed-Signal Circuit Design
0.92
article

A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing

Pranav O. Mathews, Jennifer Hasler, Swagat Bhattacharyya, Afolabi Ige, Praveen Raj Ayyappan, Linhao Yang
article en
5 citations

Abstract

Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based analog standard cell library in a commercially available 65 nm process that allows analog IC designers to use synthesis tools with an abstracted design mindset similar to large-scale digital design. We fabricate the test cells, which include filters with programmable corners, an analog classifier, and an arbitrary waveform generator (AWG); experimentally characterize FG programming; and experimentally demonstrate the performance of the standard cells. Overall, the standard cells achieve a similar or smaller footprint than previous approaches while leveraging the benefits of FG programming at smaller technology nodes.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 32(10)
Georgia Institute of Technology (US)
Affordable and clean energy
Openalex Percentile: Top 28%
Analog and Mixed-Signal Circuit Design
0.92
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A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing — Pranav O. Mathews, Jennifer Hasler, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2024) | TGRS Research Map | TGRS