A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC

In this brief, a high-gain and wide-bandwidth single-stage gain-boosted cascode amplifier (GBCA) is proposed for the front-end sample-and-hold amplifier (SHA) in 14-bit 2.5-GS/s pipelined analog-to-digital converter (ADC). This GBCA is composed of a two-layer main cascode amplifier and a three-layer cascode feedback amplifier (FA). The three-layer cascode structure introduces more than 20-dB gain enhancement compared with conventional two-layer FAs. However, adjacent poles appear near the gain bandwidth product (GBW) of the three-layer cascode FA, which may seriously deteriorate the phase margin (PM) of the FA and further prolong the settling time of closed-loop GBCA. A PM expansion technique is proposed to improve the PM of FA by adding a group of switched capacitor array. At the same time, the open-loop GBCA achieves 104-dB direct-current (dc) gain and 65.2-GHz GBW, which satisfies the harsh requirements of the ping-pong interleaved SHA with 12-dB gain on-chip. The pipelined ADC fabricated in 28-nm CMOS process consumes 554 mW at 2.5-GS/s sampling rate, while achieves a signal-to-noise-and-distortion ratio (SNDR) of 52.5 dB and a spurious free dynamic range (SFDR) of 86.4 dBc with 161-MHz input signal.

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Publication Details

Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Published
2024-08-19
DOI
https://doi.org/10.1109/tvlsi.2024.3439374
Citations
2
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.37
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article

A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC

Xubin Chen, Jiarui Liu, Yupeng Shen, Hui Xu et al.
2 citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog and Mixed-Signal Circuit Design
0.37
article

A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC

Xubin Chen, Jiarui Liu, Yupeng Shen, Hui Xu, Zhiyu Wang, Mingliang Chen, Yu Liu, Faxin Yu
article en
2 citations

Abstract

In this brief, a high-gain and wide-bandwidth single-stage gain-boosted cascode amplifier (GBCA) is proposed for the front-end sample-and-hold amplifier (SHA) in 14-bit 2.5-GS/s pipelined analog-to-digital converter (ADC). This GBCA is composed of a two-layer main cascode amplifier and a three-layer cascode feedback amplifier (FA). The three-layer cascode structure introduces more than 20-dB gain enhancement compared with conventional two-layer FAs. However, adjacent poles appear near the gain bandwidth product (GBW) of the three-layer cascode FA, which may seriously deteriorate the phase margin (PM) of the FA and further prolong the settling time of closed-loop GBCA. A PM expansion technique is proposed to improve the PM of FA by adding a group of switched capacitor array. At the same time, the open-loop GBCA achieves 104-dB direct-current (dc) gain and 65.2-GHz GBW, which satisfies the harsh requirements of the ping-pong interleaved SHA with 12-dB gain on-chip. The pipelined ADC fabricated in 28-nm CMOS process consumes 554 mW at 2.5-GS/s sampling rate, while achieves a signal-to-noise-and-distortion ratio (SNDR) of 52.5 dB and a spurious free dynamic range (SFDR) of 86.4 dBc with 161-MHz input signal.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 33(1)
Zhejiang University (CN)
Affordable and clean energy
Openalex Percentile: Top 44%
Analog and Mixed-Signal Circuit Design
0.37
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A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC — Xubin Chen, Jiarui Liu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2024) | TGRS Research Map | TGRS