Low-Power Design of Σ-Δ Modulator Utilizing FIA with Charge-Sharing Module and Two-Tap FIR Filter Embedded

This paper presents a low-power fourth-order single-bit switched capacitor sigma-delta modulator implemented by 180[Formula: see text]nm CMOS technology. In the modulator, the Floating Inverter Amplifier (FIA) with Correlated Level Shift (CLS) technique increasing gain is employed to decrease the modulators power consumption, and a two-tap Finite Impulse Response (FIR) is used in a feedback loop to reduce the integrator output swings. With the help of a simple digital circuit, the mismatches influence on the first-order integrators capacitor is mitigated because of reusing the sampling capacitor. Additionally, the work exploits the charge-sharing module to reduce the integrating capacitors size. The proposed modulator achieves 97.8[Formula: see text]dB peak Signal-to-Noise and Distortion Ratio (SNDR) at 102.4[Formula: see text]kHz over a bandwidth of 400[Formula: see text]Hz under the supply voltage of 1.2[Formula: see text]V VDD and 1.2[Formula: see text]V reference voltage while consuming a total power consumption of 3.94[Formula: see text][Formula: see text]W.