Impact of 6.5-kV SiC MOSFET Gate Bias on Reverse Recovery Over a Wide Temperature Range

This letter presents the impact of 6.5-kV silicon carbide (SiC) planar <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> negative gate bias to their reverse-recovery behavior at room temperature to 175 °C. The difference between low- and medium-voltage (MV) SiC device third-quadrant characteristics under different gate bias is introduced. The impact of negative gate bias on conductivity modulation and reverse recovery is discussed. A custom clamped-inductive load switching test setup is developed to evaluate the MV SiC device's body diode performance. Results show that the reverse recovery worsens under negative gate bias at increasingly higher temperatures. The negative gate bias leads to an increase in reverse-recovery charge and energy.