Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design

Abstract In an SRAM, threshold voltages of transistors decrease as the CMOS process technology scales down into the nanometer scale, which causes the leakage currents on the bit‐lines. The bit‐line leakage current slows reading operations or even causes reading errors. In this paper, we proposed a new scheme called RTB, which is combined with a four‐input low‐offset sense amplifier with threshold voltage consideration to solve the problem caused by bit‐line leakage current. This scheme adopts 8T cells and two pairs of bit‐lines connected to a four‐input sense amplifier to balance the bit‐line leakage current in real‐time. In this way, the maximum tolerable bit‐line leakage current can be effectively increased and the reading operation can be accelerated. Simulations in the 55 nm CMOS process design kits under different process corners, temperatures, and voltages show that the proposed scheme can increase the maximum tolerable leakage to more than 300 μA.