An improved kT/C noise cancellation technique with presampling for high‐speed SAR ADCs

Abstract The kT/C noise cancellation technique can effectively reduce the digital‐to‐analog converter (DAC) size for successive approximation register ADCs and thus relax the burden for input drivers and reference buffers. However, the prior kT/C noise cancellation technique suffers from a hard trade‐off between the noise, amplifier bandwidth and linearity. Here, an improved kT/C noise cancellation technique is proposed to break the trade‐off. It uses presampling to hold the input signal unchanged during the noise cancelling phase, leading to significantly relaxed requirements on the bandwidth and linearity of the amplifier. The proposed technique is verified in a 14‐bit 200 MS/s SAR analog‐to‐digital converter (ADC) with a DAC size of 128 fF. Simulation results show that this work achieves 75.6 dB signal to noise and distortion ratio and consumes 1.56 mW power.

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Publication Details

Journal
Electronics Letters
Published
2024-08-01
DOI
https://doi.org/10.1049/ell2.13298
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.00

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article

An improved kT/C noise cancellation technique with presampling for high‐speed SAR ADCs

Shiheng Yang, Xiaoguo Chen, Jiaxin Liu, Tiange Yi et al.
Electronics Letters
Analog and Mixed-Signal Circuit Design
article

An improved kT/C noise cancellation technique with presampling for high‐speed SAR ADCs

Shiheng Yang, Xiaoguo Chen, Jiaxin Liu, Tiange Yi, Kaipeng Wang, Yuanfan Gu
article en

Abstract

Abstract The kT/C noise cancellation technique can effectively reduce the digital‐to‐analog converter (DAC) size for successive approximation register ADCs and thus relax the burden for input drivers and reference buffers. However, the prior kT/C noise cancellation technique suffers from a hard trade‐off between the noise, amplifier bandwidth and linearity. Here, an improved kT/C noise cancellation technique is proposed to break the trade‐off. It uses presampling to hold the input signal unchanged during the noise cancelling phase, leading to significantly relaxed requirements on the bandwidth and linearity of the amplifier. The proposed technique is verified in a 14‐bit 200 MS/s SAR analog‐to‐digital converter (ADC) with a DAC size of 128 fF. Simulation results show that this work achieves 75.6 dB signal to noise and distortion ratio and consumes 1.56 mW power.

Electronics LettersVol. 60(16)
University of Electronic Science and Technology of China (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 88%
Analog and Mixed-Signal Circuit Design
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