A 0.037 pJ K2$\text{K}^2$ 338 pW temperature sensor based on dynamic leakage‐suppression logic

Abstract This letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle. The sensor effectively tackles the weak pull‐up challenge inherent in DLS logic ensuring its compatibility with standard digital logic. By capitalizing on the super cut‐off attribute of DLS logic, the frontend of the sensor achieves ultra‐low power consumption, without compromising on measurement precision or the breadth of the temperature range. The digital part of the proposed utilizes the output frequency of the sensor's frontend as the clock source, in conjunction with an external 50 Hz reference clock, achieving a low overall power consumption. The frontend of the temperature sensor was fabricated using a 180 nm process, occupying a minimal area of 374 . The digital part of the circuit is implemented using FPGA. Following a two‐point calibration and system error removal, the sensor, operating at a supply voltage of 0.8 V, demonstrated a error of across the temperature range of −20 to 125 . At 25 , the resolution figure of merit of the sensor was 0.037 pJ , with a maximum voltage sensitivity of 4.2 .