An Optimized 4-bits Absolute Value Detector

The binary absolute value detector is crucial in today's computer domain, especially in computer storage and analysis systems. It ensures the integrity and accuracy of data. Therefore, this paper proposes an optimized design of a 4-bit absolute value detector aimed at finding the circuit with the lowest energy consumption. Firstly, this paper introduces a design different from the traditional absolute value calculator, resulting in a reduced total number of stages in the circuit. Secondly, this paper calculates the delay of the main path can be using the logic effort formula and determine the specific gate sizing value for each logic component. Finally, this paper adjusts sizing and power supply ( ) ratio to achieve the lowest energy consumption at 1.5 times the minimum delay. The detector exhibits fewer critical path gates, resulting in lower average delay compared to traditional designs and features an even number of gates which means it has lower delay fluctuations across different inputs.