A Novel Switch Architecture for Multi-Die Optimization with Efficient Connections

Switches play a critical role as core components in data center networks. The advent of multi-die chiplet packaging as a prevailing trend in complex chip development presents challenges in designing the multi-die packaging of switch chips. With limited inter-die connections in mind, we propose a scalable, unified switch architecture optimized for efficient connectivity. This architecture includes the strategic mapping of data queues, meticulous planning of data paths, and the integration of a unified interface, all aiming to facilitate efficient switch operations within constrained connectivity environments. Our optimization efforts encompass various areas, including refining arbitration strategies, managing mixed unicast and multicast transmissions, and mitigating network congestion to alleviate bottlenecks in data flow. These enhancements contribute to heightened levels of performance and robustness in the switching process. During the validation phase, the structure we propose reduced interconnection usage between dies by 25%, while supporting functions such as unicast and multicast transmissions.