A 24–29.5-GHz Scalable 2 × 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems

This paper proposes a 24-29.5 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 2$ </tex-math></inline-formula> transmitter (TX) and receiver (RX) front-end chipset with streamlined intermediate frequency (IF) interfaces for digital beamforming (DBF) systems. An ultra-compact 90° coupler employing a three-dimensional (3-D) coupling structure achieves a 70% reduction in size compared to typical Lange couplers while maintaining excellent performance. This 3-D 90° coupler enables the synthesis/distribution of IF I-Q signals within the transceiver (TRX), enhancing the feasibility of mmWave DBF by reducing the demand for baseband channels and facilitating scalability for multi-beam arrays. To ensure a low-level error vector magnitude (EVM) in the TRX, the chipset employs joint package design for optimal power and noise performance. It utilizes an image-reject mixer to suppress RX image noise and introduces a DC-offset in the single-sideband up-converter for LO leakage regulation. Additionally, a frequency doubler chain is incorporated to enhance phase noise performance. Fabricated using 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m SiGe BiCMOS technology and packaged in WLCSP process, the TX achieves an average output 1-dB compression point (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$OP_{1dB}$ </tex-math></inline-formula>) of 20 dBm per channel. The RX chip features a minimum noise figure (NF) of 3.4 dB. Over-the-air (OTA) measurements conducted over a 1.1-m distance reveal a transmission data rate of up to 8 Gb/s using 16-QAM modulation at 25 GHz. Furthermore, when employing a 400-MHz 64-QAM 5G New Radio (NR) modulation, the system maintains EVM levels below -33 dB at 25 GHz and below -30 dB over 24-29.5 GHz.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2024-08-13
DOI
https://doi.org/10.1109/tcsi.2024.3438555
Citations
5
Primary Topic
Semiconductor materials and devices
Type
article
Field-Weighted Citation Impact
1.04

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article

A 24–29.5-GHz Scalable 2 × 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems

Jianyi Zhou, Long Wang, Peigen Zhou, Sidou Zheng et al.
5 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Semiconductor materials and devices
1.04
article

A 24–29.5-GHz Scalable 2 × 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems

Jianyi Zhou, Long Wang, Peigen Zhou, Sidou Zheng, Yun Hu, Xiaoyue Xia, Rui Zhou, Wei Hong, Zhe Chen, Zekun Li, Jixin Chen
article en
5 citations

Abstract

This paper proposes a 24-29.5 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 2$ </tex-math></inline-formula> transmitter (TX) and receiver (RX) front-end chipset with streamlined intermediate frequency (IF) interfaces for digital beamforming (DBF) systems. An ultra-compact 90° coupler employing a three-dimensional (3-D) coupling structure achieves a 70% reduction in size compared to typical Lange couplers while maintaining excellent performance. This 3-D 90° coupler enables the synthesis/distribution of IF I-Q signals within the transceiver (TRX), enhancing the feasibility of mmWave DBF by reducing the demand for baseband channels and facilitating scalability for multi-beam arrays. To ensure a low-level error vector magnitude (EVM) in the TRX, the chipset employs joint package design for optimal power and noise performance. It utilizes an image-reject mixer to suppress RX image noise and introduces a DC-offset in the single-sideband up-converter for LO leakage regulation. Additionally, a frequency doubler chain is incorporated to enhance phase noise performance. Fabricated using 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m SiGe BiCMOS technology and packaged in WLCSP process, the TX achieves an average output 1-dB compression point (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$OP_{1dB}$ </tex-math></inline-formula>) of 20 dBm per channel. The RX chip features a minimum noise figure (NF) of 3.4 dB. Over-the-air (OTA) measurements conducted over a 1.1-m distance reveal a transmission data rate of up to 8 Gb/s using 16-QAM modulation at 25 GHz. Furthermore, when employing a 400-MHz 64-QAM 5G New Radio (NR) modulation, the system maintains EVM levels below -33 dB at 25 GHz and below -30 dB over 24-29.5 GHz.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 72(1)
Purple Mountain Laboratories (CN), State Key Laboratory of Millimeter Waves, Southeast University (CN)
National Natural Science Foundation of China, National Key Research and Development Program of China, Fundamental Research Funds for the Central Universities
Openalex Percentile: Top 23%
Semiconductor materials and devices
1.04
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