An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process

This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed symmetric complementary switching (SCS) and split passive reference segmentation (SPRS). Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed SCS scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient SPRS is developed, which suppresses the reference settling error through the split reference segmentation. The prototype chip is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm2. Measurements show the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a 9.5-mW power consumption. The Schreier-figure-of-merit (FoM) is 175.4 dB.