Polycrystalline-Silicon CMOS Thin-Film Transistors With T-Shaped Gate and Lightly Doped Drain

We report the implementation of both n- and p-channel polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with features of T-shaped gate (T-gate) of n+ poly-Si in combination with lightly doped drain (LDD) structure. The inclusion of the T-gate and LDD structures improves both the on-state current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula>) and off-state leakage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$ </tex-math></inline-formula>) of n-channel TFTs significantly in comparison to the conventional TFTs. For p-channel poly-Si TFTs, the LDD structure mitigates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {off}}$ </tex-math></inline-formula> but leads to an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> degradation due to a potential barrier at the source junction underneath the T-gate’s wing. An additional boron channel doping not only improves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> but also adjusts the threshold voltage of p-channel TFTs. Based on our proposed poly-Si TFTs, the fabricated T-gate devices demonstrate full-swing switching of CMOS inverters.