Simulation and Fabrication of Monolithic III-V Photodetectors on Si: The Role of Growth Facets and Localization of Heterojunctions

In this work, we provide important parameters to take into account when fabricating in-plane III-V photodetectors (PDs) integrated on silicon (Si) using template-assisted selective epitaxy (TASE). Their performance has previously been demonstrated, and here, we have investigated the cause of the device-to-device variability in their current-voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i>–<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i>) characteristics. We do this by fabricating devices with variations of the geometry and analyzing their behavior by comparison with technology computer-aided design (TCAD) simulations. We demonstrate the crucial role of the crystal orientation of the substrate, which may lead to nonuniform growth rate, length, and growth front shape. With the use of TCAD simulations, we have illustrated the relevance of the position of the i-region with respect to the metal contacts of the device.