Indium-Based Flip-Chip Interconnection by Electroplating Method for Superconducting Quantum 3D Integration Architecture

This letter proposes to use electroplating method for manufacturing low cost, high volume indium bumps. The flip chip bonding process in this work supports a wide process window and has been demonstrated to reliably bonded under room temperature, 220s short duration and without protective atmosphere. As compensation for relaxing above conditions, high pressure such as 40MPa is required. Various characterization has been conducted towards In-In interconnect, including non-destructive X-ray and confocal microscopy, destructive shear strength test and cross-sectional FIB, SEM, EDS, EBSD inspection, in order to comprehensively evaluate the bonding quality from the packaging perspective. Additionally, the electrical performance of the bump chain is measured at both room and cryogenic temperature using Kelvin four-terminal method. Furthermore, magnetoresistance measuremnt is carried out under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\sim 200\sim 0$ </tex-math></inline-formula>Oe cycle at 2K for 6 times, and thermal cycling between 300K and 2K is also performed over 10 times using PPMS primarily at max rate of 20K/min, while consistently exhibiting abrupt change of resistance value near 150Oe or 3K, probably indicating the stable superconducting transition of In, suitable for future large-scale, universal quantum chiplet integration system.