An Integrated Dual-Mode Precise Bias Circuit and a Low-Noise and Wideband AFE for Fly Height Sensors in Hard Disk Drives

This paper presents the system-level discussion, simulation design, and fabrication results of a novel analog ASIC - fabricated in 130nm BiCMOS technology - for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs). FHSs are attached to the magnetic recording heads in modern hard disk drives (HDDs) to monitor the head-disk distance known as “fly height” by measuring the FHS resistance variation. The magnitude of the sensor signal serves as a measure of the proximity between the head and the disk surface which must accurately be controlled to minimize the fly height, thereby increasing the storage capacity of HDDs. The proposed interface includes two parts: 1) a dual-mode precise bias circuit that accurately provides a differential bias with a programmable common-mode voltage to the FHS in both voltage (V) and current (I) modes without requiring any calibrations, as well as featuring fast and smooth transient response, 2) front-end gain stages that create two separate signal paths with low- and high-frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface, respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I- modes to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting in an improvement of the overall noise performance of the interface. In addition, the bias noise power at the output of the LF block is suppressed to the extent of one order of magnitude thanks to deploying a noise cancellation technique. A low-noise and wide-bandwidth front-end is implemented for the HF block that eliminates the need for configuring the bias loop for having a low cutoff frequency, resulting in a reliable design with reduced complexity. Additionally, degenerated differential pairs with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process are implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2with power consumption in the range of 110 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$172~mW$ </tex-math></inline-formula> for the V-mode and 78 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$107~mW$ </tex-math></inline-formula> for the I-mode, considering typical supply voltages of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+3.3\; V$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-2.6 \;V$ </tex-math></inline-formula>, and the sensor resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{SNS} = 75\; \Omega $ </tex-math></inline-formula>) and the sensor current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{SNS}$ </tex-math></inline-formula>) from 0.5 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6\;mA$ </tex-math></inline-formula>.