A Monolithic Differential Bridged T-Coil

Two-pole and three-pole fully differential bridged T-coils applicable to wideband and high-speed integrated circuits are described. T-coil prototypes designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2 GHz and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7~{\pm }~2$ </tex-math></inline-formula> ps, respectively, across 45 GHz. The three-pole MFED design exhibits 23-GHz bandwidth and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12~{\pm }~2$ </tex-math></inline-formula>-ps group delay across 30 GHz. The bandwidth extension ratio (BWER) compared to each respective unpeaked R-C circuit is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.43\times $ </tex-math></inline-formula> (MFA) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.2\times $ </tex-math></inline-formula> (MFED). Implemented in 22-nm FD-SOI CMOS technology, the T-coil prototypes occupy a chip area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$224 \times 215~{\mu {\text {m}}^{2}}$ </tex-math></inline-formula>.