Applying Software Product Line Techniques to an Integrated Circuit System Modelling Framework: An Experience Report

Integrated circuits (ICs) are an integral part of modern electronic hardware devices. The design cycle for ICs is getting shorter and shorter as the market demands new generations of ICs that are more reliable, use less energy and are equipped with new functionalities. Additionally, only a single, first-time-right, tape-out is targeted in the design cycle to save high production costs. That means that all effort needs to be put on model-based system design and verification far before the IC enters production, validation, and customer release. As a key requirement, the IC models must predict the performance and the behavior of the IC more accurately and all possible failure modes must be identified and eliminated upfront. In this short paper, we describe how we applied Software Product Line (SPL) techniques to our existing IC model simulation framework to support these challenges. Utilizing SPL, we split the simulation flows and IC settings from the front end parameters and IC model components to manage runtime and compile time variability more efficiently. In each simulation, the front end and IC model components for the IC generation of interest are loaded. With this approach we execute a high number of simulations of multiple different parameters and settings in parallel. As a result, we simulate more scenarios in less time. We show that this approach saves our team two to three weeks when setting up new IC revisions while mitigating redundant code. Additionally, we can compile subsets of the simulation framework more easily to deploy stand-alone debugging and system design tools for internal and external customers. With this work we want the emphasize the use of SPL techniques beyond traditional software engineering domain.