Generalizable Neural Network Design Methodology of Digital Integrated Circuits for Reusable Implementations on Neuromorphic System

Deep learning with neural network could learn many features and skills to perform various tasks, including digital circuit design. Previous exploration proved that artificial neural networks can be realized into actual hardware circuit imple-mentation, improved circuit performance, as well as assisted digital circuit design process. Most of the circuit design can-not be reused, whenever there are some design modifications, the circuit creation procedures which are technical and re-source demanding will need to be repeated, which include de-signing, debugging, and testing, this can impact the overall design cost and time to market. Thus, this is critical to ex-plore a new way to expedite and simplify the digital circuit design process. This paper proposed a novel idea to demon-strate a new way of digital circuit design strategy through neural network model, which able to construct a generaliza-ble and reusable digital circuit. Neural network can learn the digital circuit functionality directly through the high-level specifications, without the dependency on the detailed specifi-cation from designers. The converged neural network model can be implemented with neuromorphic system, which has localized computation and consisted of a network of event-driven artificial neurons with parallelism capability, instead of complex standard cell logics, to achieve better efficiency in both power and computing. The finite state machine (FSM) digital circuit was used as a case study to show that its func-tionality can be learnt through recurrent neural network (RNN), which can produce flawless output prediction with consistency. We demonstrated that over 150 randomly gen-erated FSM can be learnt effectively with RNN with different levels of complexity as indicated by number of states and in-puts to the FSM. Our proposed methodology of RNN imple-mentations of FSM is generalizable and reusable, which demonstrates a way forward to reduce the cost and effort in digital circuit design.