A Fully Integrated QPSK/16-QAM <i>D</i>-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces
This work presents a fully integrated D-band transceiver (TRX) in 28-nm CMOS. The system architecture introduces a radio-frequency digital-to-analog converter (RF-DAC) and the complete mixed-signal baseband (BB) circuitry, including the equalizer, realizing fully digital BB interfaces at 24-Gb/s quadrature phase shift keying (QPSK) and 48-Gb/s 16-quadrature amplitude modulation (16-QAM). Innovations at the circuit level encompass: 1) the D-band RF front end (FE) using the proposed hybrid matching technique; 2) the two-stage conversion paths highlighting the Cartesian RF-DAC with an embedded four-tap finite impulse response (FIR) filter; 3) the local oscillator (LO) including an all-digital phase-locked loop (ADPLL) and the LO distribution network; and 4) the mixed-signal BB circuitry. The TRX achieves a transmitter (TX) bandwidth of 21 GHz, a receiver (RX) bandwidth of 18 GHz, a TX saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {sat}}$ </tex-math></inline-formula>) of 13.1 dBm, a TX output 1-dB compression point (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {OP}_{\text {1 dB}}$ </tex-math></inline-formula>) of 7.5 dBm, and an RX noise figure (NF) of 9.3 dB.
Authors
- Angxiao Yan (ORCID: https://orcid.org/0000-0002-6418-4385)
- Ruichang Ma (ORCID: https://orcid.org/0000-0002-2257-7105)
- Jiamin Xue (ORCID: https://orcid.org/0000-0002-1892-1743)
- Robert Bogdan Staszewski (ORCID: https://orcid.org/0000-0001-9848-1129)
- Teerachot Siriburanon (ORCID: https://orcid.org/0000-0003-1658-9596)
- Baoyong Chi (ORCID: https://orcid.org/0000-0003-4399-4423)
- Mingxing Deng
- Pingda Guan (ORCID: https://orcid.org/0000-0002-9296-3300)
- Wei Deng (ORCID: https://orcid.org/0000-0002-6323-4539)
- Qiuyu Peng (ORCID: https://orcid.org/0009-0001-4887-6584)
- Haikun Jia (ORCID: https://orcid.org/0000-0003-4564-8938)
- Zhihua Wang (ORCID: https://orcid.org/0000-0001-6567-0759)
- Shiyan Sun (ORCID: https://orcid.org/0000-0003-4347-505X)
Institutions
- University College Dublin (IE)
- Tsinghua University (CN)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2024-08-05
- DOI
- https://doi.org/10.1109/jssc.2024.3432759
- Citations
- 12
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 2.50
Funders
- Science Foundation Ireland
- National Key Research and Development Program of China