A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference

Compute-in-memory (CIM) is promising in reducing data movement energy and providing large bandwidth for matrix-vector multiplies (MVMs). However, existing work still faces various challenges, such as the digital logic overhead caused by the multiply-add operations (OPs) and structural sparsity. This article presents a 2-to-8-b scalable approximate digital SRAM-based CIM macro co-designed with a multiply-less neural network (NN) approach. It incorporates dynamic-logic-based approximate circuits for the logic area and energy saving by eliminating multiplications. A prototype is fabricated in 28-nm CMOS technology and achieves peak multiply-accumulate (MAC)-level energy efficiency of 102 TOPS/W for 8-b operations. The NN model deployment flow is used to demonstrate CIFAR-10 and ImageNet classification with ResNet-20 and ResNet-50 style multiply-less models, respectively, achieving the accuracy of 91.74% and 74.8% with 8-bit weights and activations.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2024-08-05
DOI
https://doi.org/10.1109/jssc.2024.3433417
Citations
13
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
2.71
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article

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference

Yuan Wang, Jiahao Song, Huazhong Yang, Wenbin Jia et al.
13 citations
IEEE Journal of Solid-State Circuits
Advanced Memory and Neural Computing
2.71
article

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference

Yuan Wang, Jiahao Song, Huazhong Yang, Wenbin Jia, Haoyang Luo, Yongpan Liu, Jinshan Yue, Haikang Diao, Xiyuan Tang, Hongyang Jia, Xuan Li, Xueqing Li, Yifan He, Chen Tang
article en
13 citations

Abstract

Compute-in-memory (CIM) is promising in reducing data movement energy and providing large bandwidth for matrix-vector multiplies (MVMs). However, existing work still faces various challenges, such as the digital logic overhead caused by the multiply-add operations (OPs) and structural sparsity. This article presents a 2-to-8-b scalable approximate digital SRAM-based CIM macro co-designed with a multiply-less neural network (NN) approach. It incorporates dynamic-logic-based approximate circuits for the logic area and energy saving by eliminating multiplications. A prototype is fabricated in 28-nm CMOS technology and achieves peak multiply-accumulate (MAC)-level energy efficiency of 102 TOPS/W for 8-b operations. The NN model deployment flow is used to demonstrate CIFAR-10 and ImageNet classification with ResNet-20 and ResNet-50 style multiply-less models, respectively, achieving the accuracy of 91.74% and 74.8% with 8-bit weights and activations.

IEEE Journal of Solid-State CircuitsVol. 60(2)
Chinese Academy of Sciences (CN), Peking University (CN), Beijing Academy of Artificial Intelligence (CN), Institute of Microelectronics (CN), Tsinghua University (CN)
Openalex Percentile: Top 9%
Advanced Memory and Neural Computing
2.71
DOISourceOpenAlex
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