Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment

Built-in speed grading (BISG) is a technique that measures the maximum operating speed (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F_{\max }$ </tex-math></inline-formula>) of a circuit under grading (CUG) in silicon. Recently, it has been reported as an effective aging sensor as well. In nowadays-chiplet-based design, the BISG circuit and the CUG could use different process technologies. In general, the BISG circuit needs to produce a clock signal with a frequency matching the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F_{\max }$ </tex-math></inline-formula> of the CUG. In this article, we discuss how to leverage an existing flexible wide-range cell-based phased-locked loop (PLL) with a frequency doubling circuit (FDC) to support even higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F_{\max }$ </tex-math></inline-formula> for a CUG that may use a more advanced technology in another die. As demonstrated in a 90 nm process, a PLL supporting a frequency range of [40 MHz, 1.25 GHz] using a mature 90 nm CMOS process can now support up to 2 GHz.