A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells.