Impact of Using Off-Chip Memories on Reliability of Edge Computing Systems to Single-Event Upsets
This work investigated the impact of using either an off-chip or an on-chip non-volatile memory on the reliability of two different RISC-V (reduced instruction set computer V) based edge computing systems operating under 14-MeV neutrons. Radiation testing results suggest the single-event upset (SEU)-induced failure rate of the case-study system with off-chip memory would be around 2.5 times higher than its counterpart with on-chip memory. Additional results of classical RISC based edge computing system running neural networks are also reported.
Authors
- Rodrigo Possamai Bastos (ORCID: https://orcid.org/0000-0002-9964-0424)
- Alberto Bosio (ORCID: https://orcid.org/0000-0001-6116-7339)
- Luiz Henrique Laurini (ORCID: https://orcid.org/0009-0008-9562-1446)
- Leonardo Alexandrino de Melo
Institutions
- Université Claude Bernard Lyon 1 (FR)
- Institut polytechnique de Grenoble (FR)
- École Centrale de Lyon (FR)
- Centre National de la Recherche Scientifique (FR)
- Institut des Nanotechnologies de Lyon (FR)
- Techniques of Informatics and Microelectronics for Integrated Systems Architecture (FR)
- Institut National des Sciences Appliquées de Lyon (FR)
- Université Grenoble Alpes (FR)
Publication Details
- Published
- 2024-09-16
- DOI
- https://doi.org/10.1109/radecs61970.2024.11298594
- Primary Topic
- Radiation Effects in Electronics
- Type
- article
- Field-Weighted Citation Impact
- 0.00