Latest Research in Hardware Architecture

Top Research Topics in Hardware Architecture

• Machine Learning — 22 papers
• Hardware Architecture — 13 papers
• Artificial Intelligence — 12 papers
• Distributed, Parallel, and Cluster Computing — 11 papers
• Computer Vision and Pattern Recognition — 7 papers
• Operating Systems — 4 papers
• Cryptography and Security — 4 papers
• Computation and Language — 4 papers
• Adversarial Robustness in Machine Learning — 2 papers
• Programming Languages — 2 papers

Highest-Cited Papers

1. Model Inversion Attacks Through Target-Specific Conditional Diffusion Models (2 citations)
2. Robustness in sparse artificial neural networks trained with adaptive topology
3. DBLP: Noise bridge consistency distillation for efficient and reliable adversarial purification
4. Information-Geometric Inverse Distillation for Enhancing Adversarial Transferability
5. LLVM Translation Validation Automated with Large Language Models and Lean
6. ECO: An LLM-Driven Efficient Code Optimizer for Warehouse Scale Computers
7. Breaking the $T^{2/3}$ Barrier for Sequential Calibration
8. VeriBugBench: An Empirically Grounded Framework for Constructing Verilog RTL Debugging Benchmarks
9. Efficient Nash Equilibrium Computation for Cybersecurity Games
10. Dual Randomized Smoothing: Beyond Global Noise Variance
11. Rethinking LLM-aided RTL Code Optimization Via Timing Logic Metamorphosis
12. SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
13. OPEN-1B: A Fully Auditable Training Run
14. CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
15. The Scissors Effect: When Resize-Based Input Diversity Helps or Hurts Transfer Attacks
16. Beyond the Previous Layer: Residual Predictive Structure in Sparse MoE Routing
17. Calibrate, Then Route: A Measured Study of Learned Request Routing for Disaggregated LLM Serving
18. Ave: Guiding Agentic GPU Optimization Using Data-Flow Invariants
19. Validating Hybrid-State Cache Recovery for GLM-5.3-Flash with vLLM and LMCache
20. LLM-enabled Behavior Driven Development Workflow for Formally Verified Hardware Designs